View CY2287_242797.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY2287
100-MHz Spread Spectrum Clock Synthesizer/Driver with USB, Hublink, and SDRAM Support
Features * Mixed 2.5V and 3.3V Operation * Multiple output clocks at different frequencies -- Three CPU clocks at 2.5V, up to 100 MHz -- Nine 3.3V SDRAM clocks at 100 MHz -- Eight synchronous PCI clocks at 33 MHz -- Two synchronous APIC clocks at 16.67 MHz or 33 MHz -- Two 3V66 clocks at 66 MHz -- Two USB clocks at 48 MHz -- One reference clock at 14.318 MHz * Spread Spectrum clocking -- 31 kHz modulation frequency -- EPROM programmable percentage of spreading -- Default is -0.6%, which is recommended by Intel(R) -- Additional options of -0.25% and -0.4% available * Power-down features * I2CTM Interface * Low skew and low jitter outputs * Test Mode * 56-pin SSOP package Benefits Usable with Pentium II, K6, and 6x86 Processors Single-chip main motherboard clock generator -- High-Speed Processor Support -- Supports Two 4-Clock SDRAM DIMMs -- Support for Six PCI Slots -- Synchronous to the CPU Clock -- Hublink Support -- Universal Serial Bus Support -- Also used as an input strap to determine APIC frequency Enables reduction of EMI
Supports mobile systems Dynamic output control Meets tight system timing requirements at high frequency Enables ATE and "bed of nails" testing Widely available, standard package enables lower cost
SSOP Top View REF0/SEL33 (14.318 MHz)
REF0/SEL33 VDDREF XTAL_IN XTAL_OUT VSSREF VSS3V66 3V66_0 3V66_1 1 2 3 4 5 6 7 8 9 10 11 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VSSAPIC APIC0 APIC1 VDDAPIC CPU0 VDDCPU CPU1 CPU2 VSSCPU VSSSDRAM SDRAM0 SDRAM1 VDDSDRAM SDRAM2 SDRAM3 VSSSDRAM SDRAM4 SDRAM5 VDDSDRAM SDRAM6 SDRAM7 VSSSDRAM SDRAM8 VDDSDRAM PWRDWN SCLK SDATA SEL1
Logic Block Diagram
CPU [0-2] (66/100 MHz)
XTALIN
XTALOUT
14.318 MHz OSC.
CPU PLL
EPROM Configurable Logic
SDRAM [0-8] (100 MHz)
VDD3V66 VDDPCI PCI0 PCI1
SEL0 SEL1
EPROM
PCI [0-7] (33MHz) APIC [0-1] (16.67/33MHz) 3V66 [0-1] (66MHz)
SYS PLL
PCI2 VSSPCI PCI3 PCI4 VSSPCI PCI5 PCI6 PCI7 VDDPCI AVDD AVSS
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
PWR_DWN
USB [0-1] (48MHz)
SCLK SDATA
SERIAL INTERFACE CONTROL LOGIC
VSSUSB USB0 USB1 VDDUSB SEL0
Intel and Pentium are registered trademarks of Intel Corporation. I2C is a trademark of Philips Corporation.
Cypress Semiconductor Corporation
*
3901 North First Street
*
San Jose
*
CA 95134
CY2287 *
12 13
408-943-2600 June 23, 1999
CY2287
Pin Summary
Name REF/SEL33 Pins 1 Description 3.3V 14.31818-MHz clock output and power-on external select strap option for APIC clock frequency. Strap LOW: APIC = PCI/2 Strap HIGH: APIC = 33.3 MHz 14.31818-MHz crystal input 14.31818-MHz crystal output 3.3V PCI clock outputs 3.3V Fixed 66.67-MHz clock outputs 3.3V Fixed 48-MHz clock outputs 3.3V LVTTL compatible inputs for logic selection 3.3V LVTTL compatible input. Device enters powerdown mode when held LOW 2.5V 66.67-MHz or 100-MHz (selectable) host bus clock output 2.5V APIC clock outputs running synchronous with PCI clock frequency. Selectable 16.67 MHz or 33.3 MHz I2C compatible SDATA input I2C compatible SCLK input 3.3V Power supply for REF output REF ground 3V66 Ground 3.3V Power supply for 3V66 outputs 3.3V Power supply for PCI outputs PCI ground 3.3V Analog power supply Analog ground USB ground 3.3V Power supply for USB outputs 3.3V Power supply for SDRAM outputs SDRAM ground CPU ground 2.5V Power supply for CPU outputs 2.5V Power supply for APIC outputs APIC ground
XTAL_IN[1] XTAL_OUT[1] PCI [0-7] 3V66 [0-1] USB [0-1] SEL [0-1] PWRDWN CPU [0-2] SDRAM [0-8] APIC [0-1] SDATA SCLK VDDREF VSSREF VSS3V66 VDD3V66 VDDPCI VSSPCI AVDD AVSS VSSUSB VDDUSB VDDSDRAM VSSSDRAM VSSCPU VDDCPU VDDAPIC VSSAPIC
3 4 11, 12, 13, 15, 16, 18, 19, 20 7, 8 25, 26 28, 29 32 49, 50, 52 54, 55 30 31 2 5 6 9 10, 21 14, 17 22 23 24 27 33, 38, 44 35, 41, 47 48 51 53 56
35, 36, 37, 39, 40, 42, 43, 45, 46 3.3V SDRAM clock outputs running 100 MHz
Note: 1. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF. For crystals with different CLOAD, please refer to the application note, "Crystal Oscillator Topics."
2
CY2287
Function Table
SEL2 0 0 0 0 1 1 1 1
[2]
SEL1 0 0 1 1 0 0 1 1
SEL0 0 1 0 1 0 1 0 1
CPU (MHz) Hi-Z TCLK /2 66.67 100 66.67 100 66.67 100
[3]
SDRAM (MHz) Hi-Z TCLK/2 100 100 100 100 100 100 SEL2[2] 0 0 X 0 0 1 1 1 1
3V66 (MHz) Hi-Z TCLK/3 66.67 66.67 66.67 66.67 66.67 66.67 SEL1 0 0 X 1 1 0 0 1 1
PCI (MHz) Hi-Z TCLK/8 33.33 33.33 33.33 33.33 33.33 33.33
USB (MHz) Hi-Z TCLK/2 48 48 48 48 48 48 SEL0 0 1 X 0 1 0 1 0 1
REF (MHz) Hi-Z TCLK 14.318 14.318 14.318 14.318 14.318 14.318
APIC[4] (MHz) Hi-Z TCLK/16 16.67 16.67 16.67 16.67 16.67 16.67
APIC [5] (MHz) Hi-Z TCLK/8 33.33 33.33 33.33 33.33 33.33 33.33
Spread Spectrum[2] X X 0 1 1 1 1 1 1
Spread Spectrum Margin N/A N/A N/A -0.6% -0.6% -0.25% -0.25% -0.4% -0.4%
Actual Clock Frequency Values
Clock Output CPUCLK CPUCLK USBCLK
Notes: 2. 3. 4. 5. Not a dedicated input pin. This selection must be addressed via I 2C interface. TCLK supplied on the XTALIN pin in Test Mode. SEL33 = LOW (power-on latch input). SEL33 = HIGH (power-on latch input).
Target Frequency (MHz) 66.67 100.0 48.0
Actual Frequency (MHz) 66.288 99.432 48.008
PPM -5230 -5680 +167
3
CY2287
Serial Configuration Map
* The Serial bits will be read by the clock driver in the following order: Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0 Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0 . . Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0 * Reserved and unused bits must be programmed to "0". * I2C Address for the CY2287 is:
Byte 2: PCI Control Register (1 = Enable, 0 = Disable) Default = Enable (for Bit [1:7]) Default = Disable (for Bit 0)
Bit Pin # PCI7 PCI6 PCI5 PCI4 PCI3 PCI2 PCI1 Reserved Description Bit 7 20 Bit 6 19 Bit 5 18 Bit 4 16 Bit 3 15 Bit 2 13 Bit 1 12 Bit 0 11
A6 1
A5 1
A4 0
A3 1
A2 0
A1 0
A0 1
R/W 0
Byte 0: Spread Spectrum, USB, SDRAM8 Control Register (1 = Enable, 0 = Disable) Default = Enable (for Bit [0:2]) Default = Disable (for Bit [3:7])
Bit Pin # Reserved Reserved Reserved SEL2 Spread Spectrum (Default = Disable) USB1 USB0 CPU2 Description Bit 7 -Bit 6 -Bit 5 -Bit4 Bit3 Bit2 Bit1 Bit0 --26 25 49
Byte 3: Peripheral Control Register (0 = Enable, 1 = Disable) Default = Enable
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 8 7 11 34 54 55 50 52 Pin # 3V66_1 3V66_0 PCI0 SDRAM8 APIC1 APIC0 CPU1 CPU0 Description
Byte 1: SDRAM Control Register (1 = Enable, 0 = Disable) Default = Enable
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 36 37 39 40 42 43 45 46 SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 Description
Byte 4: Reserved Register (0 = Enable, 1 = Disable) Default = Disable
Bit Pin # Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description Bit 7 -Bit 6 -Bit 5 -Bit 4 -Bit 3 -Bit 2 -Bit 1 -Bit 0 --
4
CY2287
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Supply Voltage ..................................................-0.5 to +7.0V Input Voltage .............................................. -0.5V to VDD+0.5 Storage Temperature (Non-Condensing) ... -65C to +150C Max. Soldering Temperature (10 sec) ...................... +260C Junction Temperature ............................................... +150C Package Power Dissipation .............................................. 1W Static Discharge Voltage (per MIL-STD-883, Method 3015) ............................. >2000V
Operating Conditions Over Which Electrical Parameters are Guaranteed
Parameter VDD3.3V VDD2.5V TA CL Description 3.3V Supply Voltages 2.5V Supply Voltages Operating Temperature, Ambient Max. Capacitive Load on CPU, USB, REF, APIC SDRAM, PCI, 3V66 Reference Frequency, Oscillator Nominal Value 14.318 Min. 3.135 2.375 0 Max. 3.465 2.625 70 20 30 14.318 MHz Unit V V C pF
f(REF)
Electrical Characteristics Over the Operating Range
Parameter VIH VIL IIH IIL IOH Description High-level Input Voltage Low-level Input Voltage Input High Current Input Low Current High-level Output Current SCLK/SDATA All inputs except SCLK/SDATA and crystal inputs SCLK/SDATA 0 < VIN < VDD 0 < VIN < VDD CPU USB, REF SDRAM PCI, 3V66 APIC IOL Low-level Output Current CPU USB, REF SDRAM PCI, 3V66 APIC IOZ IDD2 IDD3 IDDPD2 IDDPD3 Output Leakage Current 2.5V Power Supply Current 3.3V Power Supply Current 2.5V Shutdown Current 3.3V Shutdown Current Three-state AVDD/VDD33 = 3.465V, VDD25 = 2.625V, FCPU = 100 MHz AVDD/VDD33 = 3.465V, VDD25 = 2.625V, FCPU = 100 MHz AVDD/VDD33 = 3.465V, VDD25 = 2.625V
[7] [7] [6]
Test Conditions All inputs except SCLK/SDATA and crystal inputs[6]
Min. 2.0 0.7
Typ
Max. Unit V VDD 0.8 0.3 V VDD A A mA
-10 -10 VOH = 2.0V VOH = 2.4V VOH = 2.4V VOH = 2.4V VOH = 2.0V VOL = 0.4V VOL = 0.4V VOL = 0.4V VOL = 0.4V VOL = 0.4V -16 -15 -30 -30 -16 19 10 20 20 19
+10 +10 -60 -51 -100 -100 -60 49 24 49 49 49 10 100 280 <1 <9 500 500
mA
A mA mA A A
AVDD/VDDQ3 = 3.465V, V DD25 = 2.625V
Notes: 6. Crystal inputs have CMOS thresholds, nominally VDD/2. 7. Tested @ 500 A. Actual performance is much better. Call Cypress if tighter spec is required.
5
CY2287
CY2287 Switching Characteristics[8] Over the Operating Range
Parameter t1 t2 t2 t2 t2 t3 t3 t3 t3 t4 t4 t4 t4 t4 t4 t4 t5 t6_66 t6_100 t7_66 t7_100 t8 t8 t8 t8 t8 t8 tSTABLE All CPU, APIC USB, REF PCI, 3V66 SDRAM CPU, APIC USB, REF PCI, 3V66 SDRAM CPU SDRAM APIC PCI 3V66 3V66, PCI APIC, PCI SDRAM, 3V66 CPU, 3V66 CPU, 3V66 CPU, SDRAM CPU, SDRAM CPU SDRAM APIC USB 3V66 REF All Outputs Output Description Output Duty Cycle Rising Edge Rate Rising Edge Rate Rising Edge Rate Rising Edge Rate Falling Edge Rate Falling Edge Rate Falling Edge Rate Falling Edge Rate CPU-CPU Skew SDRAM-SDRAM Skew APIC-APIC Skew PCI-PCI Skew 3V66-3V66 Skew 3V66-PCI Clock Skew APIC-PCI Clock Skew SDRAM-3V66 Clock Skew CPU-3V66 Clock Skew CPU-3V66 Clock Skew CPU-SDRAM Clock Skew CPU-SDRAM Clock Skew Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Cycle-Cycle Clock Jitter Settle Time
[9]
Test Conditions t1A/(t1A + t1B) Between 0.4V and 2.0V Between 0.4V and 2.4V Between 0.4V and 2.4V Between 0.4V and 2.4V Between 2.0V and 0.4V Between 2.4V and 0.4V Between 2.4V and 0.4V Between 2.4V and 0.4V Measured at 1.25V Measured at 1.5V Measured at 1.25V Measured at 1.5V Measured at 1.5V 3V66 leads
[10] [10, 11] [10]
Min. 45 1.0 0.5 1.0 1.0 1.0 0.5 1.0 1.0
Max. 55 4.0 2.0 4.0 4.0 4.0 2.0 4.0 4.0 175 250 250 500 175
Unit % V/ns V/ns V/ns V/ns V/ns V/ns V/ns V/ns ps ps ps ps ps ns ps ps ns ps ns ns ps ps ps ps ps ps ms
1.5
4.0 500 500
Coincident every edge CPU leads[10]
Coincident every other 3V66 edge Coincident every other 3V66 edge SDRAM leads
[10, 12]
7.0
[10]
8.0 500 3.0 5.5 250 250 500 500 500 1000 3
2.0
[10]
CPU leads, measured every edge Measured at 1.25V, t8A - t8B Measured at 1.5V, t8A - t8B Measured at 1.25V, t8A - t8B Measured at 1.5V, t8A - t8B Measured at 1.5V, t8A - t8B Measured at 1.5V, t8A - t8B
4.5
All clock stabilization from power-up
Notes: 8. All parameters specified with loaded outputs as follows: CPU, APIC, REF, USB = 12.5 pF: SDRAM, 3V66, PCI=20 pF. 9. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. 10. Measured at 1.25V for 2.5V clocks and 1.5V for 3.3V clocks. 11. Coincident every other APIC edge if APIC running at 16 MHz. 12. Measured every third CPU edge.
6
CY2287
Switching Waveforms
Duty Cycle Timing
t1A t1B
All Outputs Rise/Fall Time
VDD OUTPUT 0V t2 t3
CLK-CLK Output Skew
CLKA
CLKB t4
Cycle-Cycle Clock Jitter
t8A t8B
CLK
[13, 14, 15]
PWR_DOWN
CPUCLK Peripheral Clocks PWR_DWN VCO Crystal
Notes: 13. Once the PWR_DWN signal is sampled LOW for two consecutive rising edges of CPU clock, clocks of interest will be held LOW on the next HIGH-to-LOW transition. 14. Waveforms are not to scale. 15. Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.
7
CY2287
Switching Waveforms (continued)
CLK-CLK Output Skew (CPU @ 66 MHz)
0 ns 10 ns 20 ns 30 ns 40 ns
CPU 66 MHz SDRAM 100 MHz
t5
3V66 66 MHz SDRAM to 3V66 Skew, SDRAM leads 3V66 by 0.0 ns (500-ps window)
CLK-CLK Output Skew (CPU @ 66 MHz)
0 ns 10 ns 20 ns 30 ns 40 ns
CPU 66 MHz
t6_66
3V66 66 MHz SDRAM 100 MHz CPU to 3V66 Skew, CPU leads 3V66 by 7.5ns (500-ps window) CLK-CLK Output Skew (CPU @ 66 MHz)
0 ns 10 ns 20 ns 30 ns 40 ns
CPU 66 MHz SDRAM 100 MHz 3V66 66 MHz
t7_66
CPU to SDRAM Skew, SDRAM leads CPU by 2.5 ns (500-ps window)
8
CY2287
Switching Waveforms (continued)
CLK-CLK Output Skew (CPU @ 100 MHz)
0 ns 10 ns 20 ns 30 ns 40 ns
CPU 100 MHz SDRAM 100 MHz
t5
3V66 66 MHz SDRAM to 3V66 Skew, SDRAM leads 3V66 by 0.0 ns (500-ps window)
CLK-CLK Output Skew (CPU @ 100 MHz)
0 ns 10 ns 20 ns 30 ns 40 ns
CPU 100 MHz 3V66 66 MHz SDRAM 100 MHz
t 6_100
CPU to 3V66 Skew, CPU leads 3V66 by 0.0 ns (500-ps window)
CLK-CLK Output Skew (CPU @ 100 MHz)
0 ns 10 ns 20 ns 30 ns 40 ns
CPU 100 MHz SDRAM 100 MHz 3V66 66 MHz
t7_100
CPU to SRAM Skew, CPU leads SDRAM by 5.0 ns (500-ps window)
9
CY2287
Switching Waveforms (continued)
Window Measurement Clarification
500-ps window
Earliest of Group A 1.5V
Group A
1.5V
Group B
Latest of Group B
Example of SDRAM to 3V66 Skew Measurement (CPU @ 66 or 100 MHz) SDRAM leads 3V66 by 0.0 ns (500-ps window)
Window Measurement Clarification
8.0-ns window (max) 7.0-ns window (min)
Earliest of CPU Group 1.25V
Latest of CPU Group
CPU Group
Earliest of 3V66 Group
1.5V
3V66 Group
Latest of 3V66 Group
Example of CPU to 3V66 Skew Measurement (CPU @ 66 MHz) CPU leads 3V66 by 7.5 ns (500-ps window)
10
CY2287
Switching Waveforms (continued)
SPREAD SPECTRUM CLOCKING
Description Modulation Frequency Down Spread Margin at the Fundamental Frequency Output CPU, PCI, SDRAM, APIC, 3V66 CPU, PCI, SDRAM, APIC, 3V66 Min. 30.0 -0.25 Max. 33.0 -0.6 Unit kHz %
Spread Spectrum Disabled
Spread Spectrum Enabled
Amplitude (dB)
Selectable Downspread Margins -0.25% -0.4% -0.6%
Frequency (MHz)
11
CY2287
Application Information
Clock traces must be terminated with either series or parallel termination, as they are normally done.
Application Circuit
XTALIN XTALOUT
Cx Rs
SEL0 SEL1 PWR_DWN SEL0 SEL1 PWR_DWN CPU SDRAM PCI HUBLINK APIC REF USB CPU SDRAM PCI 3V66 APIC REF USB
3.3V VDD VDD3.3V
Cd Ct
2.5V VDD VDD2.5V
Cd
VSS
CY2287-1 56 Pin SSOP Cd = Decoupling Capacitors (NOTE: May use 0.1F, but value will vary with frequency of operation and output current) Ct = Optional EMI-Reducing Capacitors Cx = Optional Load Matching Capacitors Rs = Termination Resistor
Summary
* A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different CLOAD is used. Footprints must be laid out for flexibility. * Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 2.2 nF. In some cases, smaller value capacitors may be required. * The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the clock generator (CPU/APIC = 29 Ohm, USB/REF = 40 Ohm, SDRAM (3.3V)= 16 Ohm, PCI/3V66 = 30 Ohm - all nominal driver output impedances), and Rseries is the series terminating resistor. Rseries > R trace - Rout * Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. * A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50 impedance at the clock frequency, under loaded DC conditions. Please refer to the application note "Layout and Termination Techniques for Cypress Clock Generators" for more details. * If a Ferrite Bead is used, a 10 F- 22 F tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges.
12
CY2287: May 26, 1998 Revision: June 23, 1999
CY2287
Test Circuit
VDD3.3V 5, 6, 14, 17, 23, 24, 34, 41, 47, 48, 56 2, 9, 10, 21, 22, 27, 32, 38, 44 CY2287 OUTPUTS 51, 53 CLOAD
VDD2.5V
Note: Each supply pin must have an individual decoupling capacitor. Note: All capacitors must be placed as close to the pins as is physically possible.
Ordering Information
Ordering Code CY2287PVC-1 Document #: 38-00711-A Package Name O56 Package Type 56-Pin SSOP Operating Range Commercial
Package Diagram
56-Lead Shrunk Small Outline Package O56
51-85062-B
(c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

▲Up To Search▲

Price & Availability of CY2287

	To Download CY2287 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .